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PRELIMINARY
PCI EXPRESSTM CLOCK GENERATOR
ICS841S01
GENERAL DESCRIPTION
The ICS841S01 is a PLL-based clock generator IC S specifically designed for PCI_ExpressTMClock HiPerClockSTM Generation applications. This device generates a 100MHz HCSL clock. The device offers a HCSL (Host Clock Signal Level) clock output from a clock input reference of 25MHz. The input reference may be derived from an external source or by the addition of a 25MHz crystal to the on-chip crystal oscillator. An external reference may be applied to the XTAL_IN pin with the XTAL_OUT pin left floating. The device offers spread spectrum clock output for reduced EMI applications. An I2C bus interface is used to enable or disable spread spectrum operation as well as select either a down spread value of -0.35% or -0.5%. The ICS841S01 is available in both standard and lead-free 16-Lead TSSOP packages.
FEATURES
* One 0.7V current mode differential HCSL output pair * Crystal oscillator interface, 25MHz * Output frequency: 100MHz * RMS period jitter: 3ps (maximum) * Cycle-to-cyle jitter: 35ps (maximum) * I2C support with readback capabilities up to 400kHz * Spread Spectrum for electromagnetic interference (EMI) reduction * 3.3V operating supply mode * 0C to 70C ambient operating temperature * Available in both standard (RoHS 5) and lead-free (RoHS 6) packages
BLOCK DIAGRAM
25MHz
PIN ASSIGNMENT
PLL Divider Network
SRCT0 SRCC0
XTAL_IN
OSC
XTAL_OUT SDATA Pullup SCLK Pullup
I2C Logic
VSS_SRC VDD_SRC SRCT0 SRCC0 VDD_SRC VSS_SRC IREF VSSA
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VDD_SRC SDATA SCLK XTAL_OUT XTAL_IN VDD_REF VSS_REF VDDA
ICS841S01
IREF
16-Lead TSSOP 4.4mm x 5.0mm x 0.92mm package body G Package Top View
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
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TABLE 1. PIN DESCRIPTIONS
Number 1, 6 2, 5, 16 3, 4 7 8 9 10 11 12, 13 Name VSS_SRC VDD_SRC SRCT0, SRCC0 IREF VSSA VDDA VSS_REF VDD_REF Type Power Power Output Input Power Power Power Power Description Ground for core and SRC outputs. Power supply for core and SRC outputs. Differential output pair. HCSL interface levels. A fixed precision resistor (475) from this pin to ground provides a reference current used for differential current-mode SRCC0, SRCT0 clock outputs. Analog ground pin. Power supply for PLL. Ground for crystal interface
Power supply for crystal interface. Crystal oscillator interface. XTAL_IN is the input. XTAL_IN, XTAL_OUT Input XTAL_OUT is the output. SMBus compatible SCLK. This pin has an internal pullup resistor, but 14 SCLK Input Pullup is in high impedance in powerdown mode. LVCMOS/LVTTL interface levels. SMBus compatible SDATA. This pin has an internal pullup resistor, Input/ Pullup but is in high impedance in powerdown mode. 15 SDATA Output LVCMOS/LVTTL interface levels. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP COUT Parameter Input Capacitance Input Pullup Resistor Output Pin Capacitance Test Conditions Minimum Typical 4 51 4 Maximum Units pF k pF
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SERIAL DATA INTERFACE
To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initialize to their default setting upon power-up, and therefore, use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface cannot be used during system operation for power management functions.
DATA PROTOCOL
The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 3A. The block write and block read protocol is outlined in Table 3B, while Table 3C outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h).
TABLE 3A. COMMAND CODE DEFINITION
BIT 7 6:5 4:0 Description 0 = Block read or block write operation, 1 = Byte read or byte write operation. Chip select address, set to "00" to access device. Byte offset for byte read or byte write operation. For block read or block write operations, these bits must be "00000".
TABLE 3B. BLOCK READ AND BLOCK WRITE PROTOCOL
BIT 1 2:8 9 10 11:18 19 20:27 28 29:36 37 38:45 46 Description = Block Write Star t Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits Acknowledge from slave Byte Count - 8 bits Acknowledge from slave Data byte 1 - 8 bits Acknowledge from slave Data byte 2 - 8 bits Acknowledge from slave Data Byte/Slave Acknowledges Data Byte N - 8 bits Acknowledge from slave Stop BIT 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39:46 47 48:55 56 Description = Block Read Star t Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits Acknowledge from slave Repeat star t Slave address - 7 bits Read = 1 Acknowledge from slave Byte Count from slave - 8 bits Acknowledge Data Byte 1 from slave - 8 bits Acknowledge Data Byte 2 from slave - 8 bits Acknowledge Data Bytes from Slave / Acknowledges Data Byte N from slave - 8 bits Not Acknowledge
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TABLE 3C. BYTE READ AND BYTE WRITE PROTOCOL
BIT 1 2:8 9 10 11:18 19 20:27 28 29 Description = Byte Write Star t Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits Acknowledge from slave Data byte - 8 bits Acknowledge from slave Stop BI T 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39 Description = Byte Read Star t Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits Acknowledge from slave Repeat star t Slave address - 7 bits Read Acknowledge from slave Data from slave - 8 bits Not Acknowledge Stop
CONTROL REGISTERS
TABLE 4A. BYTE 0:CONTROL REGISTER 0
BIT 7 6 5 4 3 2 1 0 @Pup 0 1 1 1 1 1 0 0 Name Reser ved Reser ved Reser ved Reser ved Reser ved SRC[T/C]0 Reser ved Reser ved Description Reser ved Reser ved Reser ved Reser ved Reser ved SRC[T/C]0 Output Enable 0 = Disable (Hi-Z) 1 = Enable Reser ved Reser ved
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TABLE 4B. BYTE 1:CONTROL REGISTER 1
BIT 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Name Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Description Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved
TABLE 4C. BYTE 2:CONTROL REGISTER 2
BIT 7 6 5 4 3 2 1 0 @Pup 1 1 1 0 1 0 1 1 Name SRCT/C Reser ved Reser ved Reser ved Reser ved SRC Reser ved Reser ved Description Spread Spectrum Selection 0 = -0.35%, 1 = -0.50% Reser ved Reser ved Reser ved Reser ved SRC Spread Spectrum Enable 0 = Spread Off, 1 = Spread On Reser ved Reser ved
TABLE 4D. BYTE 3:CONTROL REGISTER 3
BIT 7 6 5 4 3 2 1 0 @Pup 1 0 1 0 1 1 1 1 Name Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Description Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved
TABLE 4E. BYTE 4:CONTROL REGISTER 4
BIT 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 1 Name Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Description Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved
TABLE 4F. BYTE 5:CONTROL REGISTER 5
BIT 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Name Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Description Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved
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TABLE 4G. BYTE 6:CONTROL REGISTER 6
BIT 7 6 5 4 3 2 1 0 @Pup 0 0 0 1 0 0 1 1 Name TEST_SEL TEST_MODE Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Description REF/N or Hi-Z Select 0 = Hi-Z, 1 = REF/N TEST Clock Mode Entr y Control 0 = Normal Operation, 1 = REF/N or Hi-Z Mode Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved
TABLE 4H. BYTE 7:CONTROL REGISTER 7
BIT 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 1 Name Description Revision Code Bit Revision Code Bit Revision Code Bit Revision Code Bit Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 3 2 1 0
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ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO 4.6V -0.5V to VDD_REF + 0.5 V -0.5V to VDD_SRC + 0.5V NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Package Thermal Impedance, JA 89C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C
TABLE 5A. POWER SUPPLY DC CHARACTERISTICS, VDD_REF = VDDA = VDD_SRC = 3.3V5%, TA = TA = 0C TO 70C
Symbol VDD_REF VDDA VDD_SRC IDD_REF IDDA IDD_SRC Parameter Power Supply Voltage Analog Supply Voltage Core/SRC Output Supply Voltage Cr ystal Supply Current Analog Supply Current Core/SRC Supply Current Test Conditions Minimum 3.135 VDD_REF - 0.25 3.135 Typical 3.3 3.3 3. 3 Maximum 3.465 VDD_REF 3.465 8 25 130 Units V V V mA mA mA
TABLE 5B. DC CHARACTERISTICS, VDD_REF = VDDA = VDD_SRC = 3.3V5%, TA = TA = 0C TO 70C
Symbol Parameter VIHSMBUS Input High Voltage VILSMBUS IIH IIL IOH IOZ Input Low Voltage Input High Current Input Low Current Output Current High Impedance Leakage Current -10 Test Conditions SDATA, SCLK SDATA, SCLK SDATA, SCLK SDATA, SCLK VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V -150 14 10 Minimum Typical 2.2 Maximum 1.0 5 Units V V A A mA A
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TABLE 6. AC CHARACTERISTICS, VDD_REF = VDDA = VDD_SRC = 3.3V5%, TA = 0C TO 70C
Symbol Parameter fref sclk Frequency SCLK Frequency Frequency Tolerance; NOTE 1 odc tPERIOD tjit(cc) tjit(per) tR / tF tRFM tDC tR / tF VHIGH VLOW VOX VOVS VUDS XTAL External Reference SRCT/SRCC Duty Cycle; NOTE 2, 7 Average Period; NOTE 3 SRCT/C Cycle-to-Cycle Jitter; NOTE 2, 7 Period Jitter, RMS; NOTE 2, 7 SRCT/SRCC Rise/Fall Time; NOTE 4 Rise/Fall Time Matching; NOTE 5 XTAL_IN Duty Cycle; NOTE 6 Rise/Fall Time Variation Voltage High Voltage Low Output Crossover Voltage Maximum Overshoot Voltage Minimum Undershoot Voltage -0.3 @ 0.7V Swing 520 -150 250 550 VHIGH + 0.3 47.5 20% to 80% 175 Test Conditions Minimum Typical 25 400 50 0 47 9.9970 53 10.0533 35 3 700 20 52.5 125 800 Maximum Units MHz kHz ppm ppm % ns ps ps ps % % ps mv mv mV V V
Ring Back Voltage 0.2 V VRB NOTE 1: With recommended crystal. NOTE 2: Measured at crossing point VOX. NOTE 3: Measured at crossing point VOX at 100MHz. NOTE 4: Measured from VOL = 0.175V to VOH = 0.525V. NOTE 5: Determined as a fraction of 2*(tR - tF) / (tR + tF). NOTE 6: The device will operate reliably with input duty cycles up to 30/70% but the REF clock duty cycle will not be within specification NOTE 7: Measured using a 50 to GND termination.
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PARAMETER MEASUREMENT INFORMATION
3.3V5% 3.3V5%
Measurement Point
VDD_REF, VDD_SRC
33
100
SRCC0 SRCT0
tcycle n tcycle
VDDA
49.9 2pF 100 Measurement Point
HCSL
33 GND 475 49.9
2pF
tjit(cc) = tcycle n - tcycle n+1 1000 Cycles
0V
3.3V HCSL OUTPUT LOAD AC TEST CIRCUIT
CYCLE-TO-CYCLE JITTER
VOH VREF VOL
nSRCx SRCx
nSRCy SRCy
1 contains 68.26% of all measurements 2 contains 95.4% of all measurements 3 contains 99.73% of all measurements 4 contains 99.99366% of all measurements 6 contains (100-1.973x10-7)% of all measurements
tsk(o)
Histogram
Reference Point
(Trigger Edge)
Mean Period
(First edge after trigger)
RMS PERIOD JITTER
OUTPUT SKEW
SRCC0
80%
SRCT0
t PW
t
PERIOD
Clock Outputs
x 100%
20% tR tF
odc =
t PW t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
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tcycle n+1 tcycle n+1
80% VSW I N G 20%
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APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS841S01 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD_REF, VDDA, and VDD_SRC should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VDDA pin. The 10 resistor can also be replaced by a ferrite bead.
3.3V VDD .01F VDDA .01F 10F 10
FIGURE 1. POWER SUPPLY FILTERING
USING THE ON-BOARD CRYSTAL OSCILLATOR
The ICS841S01 features a fully integrated Pierce oscillator to minimize system implementation costs. The ICS841S02I may be operated with a 25MHz crystal and without additional components. Recommended operation for the crystal should be of a parallel resonant type and a load specification of CL = 18pF. See Table 7 for complete crystal specifications. If more precise frequency control is desired, the addition of capacitors from each of the XTAL_IN and XTAL_OUT pins to ground may be used to trim the frequency as shown in Figure 2. 25MHz The crystal and optional trim capacitors should be located as close to the ICS841S01 XTAL_IN and XTAL_OUT pins as possible to avoid any board level parasitic.
XT AL_IN
33pF TBD
TABLE 7. RECOMMENDED CRYSTAL SPECIFICATIONS
Parameter Crystal Cut Resonance Shunt Capacitance (CL) Load Capacitance (CO) Equivalent Series Resistance (ESR) Value Fundamental AT Cut Parallel Resonance 5-7pF 18pF 20-50
TBD 18pF XTAL_OUT
FIGURE 2. CRYSTAL OSCILLATOR WITH TRIM CAPACITOR
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RECOMMENDATIONS FOR UNUSED INPUT PINS INPUTS:
LVCMOS CONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used.
OUTPUT DRIVER CURRENT
The ICS841S01 outputs are HCSL current drive with the current being set with a resistor from IREF to ground. For a 50 pc board trace, the drive current would typically be set with a RREF of 475 which products an IREF of 2.32mA. The IREF is multiplied by a current mirror to an output drive of 6*2.32mA or 13.92mA. See Figure 3 for current mirror and output drive details.
IREF
RREF
RL
RL
FIGURE 3. HCSL CURRENT MIRROR
AND
OUTPUT DRIVE
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RECOMMENDED TERMINATION
Figure 4A is the recommended termination for applications which require the receiver and driver to be on a separate PCB. All traces should be 50 impedance.
FIGURE 4A. RECOMMENDED TERMINATION
Figure 4B is the recommended termination for applications which require a point to point connection and contain the driver
and receiver on the same PCB. All traces should all be 50 impedance.
FIGURE 4B. RECOMMENDED TERMINATION
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RELIABILITY INFORMATION
TABLE 8. JAVS. AIR FLOW TABLE
FOR
16 LEAD TSSOP
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 137.1C/W 89.0C/W
200
118.2C/W 81.8C/W
500
106.8C/W 78.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS841S02 is: 1874
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PACKAGE OUTLINE - G SUFFIX FOR 16 LEAD TSSOP
TABLE 9. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 -0.05 0.80 0.19 0.09 4.90 6.40 BASIC 4.50 0.65 BASIC 0.75 8 0.10 Millimeters Minimum 16 1.20 0.15 1.05 0.30 0.20 5.10 Maximum
Reference Document: JEDEC Publication 95, MO-153
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TABLE 10. ORDERING INFORMATION
Part/Order Number ICS841S01BG ICS841S01BGT ICS841S01BGLF ICS841S01BGLFT NOTE: Par ts that are ordered Marking Package Shipping Packaging Temperature 841S01BG 16 Lead TSSOP tube 0C to 70C 841S01BG 16 Lead TSSOP 2500 tape & reel 0C to 70C 841S01BL 16 Lead "Lead-Free" TSSOP tube 0C to 70C 841S01BL 16 Lead "Lead-Free" TSSOP 2500 tape & reel 0C to 70C with an"LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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(c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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